Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology

نویسندگان

چکیده

Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects potential applications in Integrated Circuit (IC) industry. MOS Current Mode Logic (MCML) based implementations with rapid response simultaneous generation of complemented output is all set to become indispensable nano regime This paper attempts optimize address performance-based analysis NAND, D flipflop 3-bit asynchronous counter by practicing MCML implementation. These are contemplated on four design parameters delay (t_p), power (pwr), Power Delay Product (PDP) Energy (EDP). research focuses relative emanate a salient optimal application Complementary Metal-Oxide-Semiconductor (CMOS) Carbon Nanotube Field Effect Transistor (CNFET) counter. In addition this, the two configurations then compared against applied V_DD at 16-nm technology nodes using HSPICE simulator. CNFET observed be much faster (9.75x), significant improvement gross dissipation (11.93x), material refinement PDP EDP (116.39x 1165x) respectively as conventional counterpart. Therefore, comes fore resilient supporting high level integration scale regime.

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Low Power Asynchronous UP Counter using CNTFET

In many applications counter is used to divide input clock to produce output, the frequency of the output is the divide by N times of the input clock frequency. Due to these reasons ripple counters can be used as frequency dividers to reduce a high clock frequency down to a more usable value for use in digital clocks and timing applications. In many applications such as ultra low power digital ...

متن کامل

Power Optimized Counter Based Clock Design Using Pass Transistor Technique

This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be desingned by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical pat...

متن کامل

a low-power and low-energy 1-bit full adder cell using 32nm cnfet technology node

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

متن کامل

Design and Implementation of Bit Transition Counter

In today’s VLSI system design, power consumption is gaining more attention as compared to performance and area. This is due to battery life in portable devices and operating frequency of the design. Power consumption mainly consists of static power, dynamic power, leakage power and short circuit power. Dynamic power is dominant among all which depends on many factors viz. power supply, load cap...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Advances in Electrical and Electronic Engineering

سال: 2022

ISSN: ['1804-3119', '1336-1376']

DOI: https://doi.org/10.15598/aeee.v20i3.4279